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MM54C192 MM74C192 Synchronous 4-Bit Up Down Decade Counter MM54C193 MM74C193 Synchronous 4-Bit Up Down Binary Counter
February 1988
MM54C192 MM74C192 Synchronous 4-Bit Up Down Decade Counter MM54C193 MM74C193 Synchronous 4-Bit Up Down Binary Counter
General Description
These up down counters are monolithic complementary MOS (CMOS) integrated circuits The MM54C192 and www..com MM74C192 are BCD counters while the MM54C193 and MM74C193 are binary counters Counting up and counting down is performed by two count inputs one being held high while the other is clocked The outputs change on the positive-going transition of this clock These counters feature preset inputs that are set when load is a logical ``0'' and a clear which forces all outputs to ``0'' when it is at a logical ``1'' The counters also have carry and borrow outputs so that they can be cascaded using no external circuitry
Features
Y Y Y Y Y Y
High noise margin 1V guaranteed Tenth power TTL compatible Drive 2 LPTTL loads Wide supply range 3V to 15V Carry and borrow outputs for N-bit cascading Asynchronous clear High noise immunity 0 45 VCC (typ )
Connection Diagram
Dual-In-Line Package
TL F 5901 - 1
Top View Order Number MM54C192 MM74C192 MM54C193 or MM74C193
C1995 National Semiconductor Corporation
TL F 5901
RRD-B30M105 Printed in U S A
Absolute Maximum Ratings (Note 1)
If Military Aerospace specified devices are required please contact the National Semiconductor Sales Office Distributors for availability and specifications Voltage at Any Pin Operating Temperature Range (TA) MM54C154 MM74C154
b 0 3V to VCC a 0 3V b 55 C to a 125 C b 40 C to a 85 C
Storage Temperature Range (TS) Maximum VCC Voltage Power Dissipation (PD) Dual-In-Line Small Outline Operating VCC Range Lead Temperature (TA) (Soldering 10 sec )
b 65 C to a 150 C
18V 700 mW 500 mW 3V to 15V 260 C
DC Electrical Characteristics Min
Symbol CMOS TO CMOS Parameter
Max limits apply across temperature range unless otherwise noted Conditions Min Typ Max Units
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IN(1)
Logical ``1'' Input Voltage Logical ``0'' Input Voltage Logical ``1'' Output Voltage Logical ``0'' Output Voltage Logical ``1'' Input Current Logical ``0'' Input Current Supply Current
VCC e 5V VCC e 10V VCC e 5V VCC e 10V VCC e 5V IO e b10 mA VCC e 10V IO e b10 mA VCC e 5V IO e 10 mA VCC e 10V IO e 10 mA VCC e 15V VIN e 15V VCC e 15V VIN e 0V VCC e 15V
35 80 15 20 45 90 05 10 0 005
b1 0 b 0 005
V V V V V V V V mA mA 300 mA
VIN(0) VOUT(1) VOUT(0) IIN(1) IIN(0) ICC
10
0 05
CMOS TO LPTTL INTERFACE VIN(1) VIN(0) VOUT(1) VOUT(0) Logical ``1'' Input Voltage Logical ``0'' Input Voltage Logical ``1'' Output Voltage Logical ``0'' Output Voltage 54C VCC e 4 5V 74C VCC e 4 75V 54C VCC e 4 5V 74C VCC e 4 75V 54C VCC e 4 5V IO e b100 mA 74C VCC e 4 75V IO e b100 mA 54C VCC e 4 5V IO e 360 mA 74C VCC e 4 75V IO e 360 mA 24 24 04 04 VCC b 1 5 VCC b 1 5 08 08 V V V V V V V V
OUTPUT DRIVE (See 54C 74C Family Characteristics Data Sheet) (Short Circuit Current) ISOURCE ISOURCE ISINK ISINK Output Source Current Output Source Current Output Sink Current Output Sink Current VCC e 5V VIN(0) e 0V TA e 25 C VOUT e 0V VCC e 10V VIN(0) e 0V TA e 25 C VOUT e 0V VCC e 5V VIN(1) e 5V TA e 25 C VOUT e VCC VCC e 10V VIN(1) e 10V TA e 25 C VOUT e VCC
b 1 75 b8
mA mA mA mA
1 75 8
Note 1 ``Absolute Maximum Ratings'' are those values beyond which the safety of the device cannot be guaranteed Except for ``Operating Temperature Range'' they are not meant to imply that the devices should be operated at these limits The table of ``Electrical Characteristics'' provides conditions for actual device operation
2
AC Electrical Characteristics
Symbol tpd tpd tpd tS tW tW tpd0 tpd1 tW fMAX tr tf CIN CPD Parameter Propagation Delay Time to Q from Count Up or Down Propagation Delay Time to Q Borrow from Count Down Propagation Delay Time to Carry from Count Up Time Prior to Load that Data Must be Present Minimum Clear Pulse Width Minimum Load Pulse Width Propagation Delay Time to Q from Load Minimum Count Pulse Width Maximum Count Frequency Count Rise and Fall Time Input Capacitance Power Dissipation Capacitance
TA e 25 C CL e 50 pF unless otherwise noted Conditions VCC e 5V VCC e 10V VCC e 5V VCC e 10V VCC e 5V VCC e 10V VCC e 5V VCC e 10V VCC e 5V VCC e 10V VCC e 5V VCC e 10V VCC e 5V VCC e 10V VCC e 5V VCC e 10V VCC e 5V VCC e 10V VCC e 5V VCC e 10V (Note 2) (Note 3) 5 100 25 6 Min Typ 250 100 120 50 120 50 100 30 300 120 100 40 300 120 120 35 4 10 15 5 Max 400 160 200 80 200 80 160 50 480 190 160 65 480 190 200 80 Units ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns MHz MHz ms ms pF pF
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AC Parameters are guaranteed by DC correlated testing Note 1 ``Absolute Maximum Ratings'' are those values beyond which the safety of the device cannot be guaranteed Except for ``Operating Temperature Range'' they are not meant to imply that the devices should be operated at these limits The table of ``Electrical Characteristics'' provides conditions for actual device operation Note 2 Capacitance is guaranteed by periodic testing Note 3 CPD determines the no load AC power consumption of any CMOS device For complete explanation see 54C 74C Family Characteristics Application Note AN-90
Cascading Packages
Guaranteed Noise Margin as a Function of VCC
TL F 5901 - 3 TL F 5901 - 2
3
Timing Diagrams
MM54C192 MM74C192
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TL F 5901 - 4
Note 1 Clear ouptuts to zero Note 2 Load (preset) to binary thirteen Note 3 Count up to fourteen fifteen carry zero one and two Note 4 Count down to one zero borrow fifteen fourteen and thirteen
MM54C193 MM74C193
TL F 5901 - 5
Note 1 Clear ouptuts to zero Note 2 Load (preset) to BCD seven Note 3 Count up to eight nine carry zero one and two Note 4 Count down to one zero borrow nine eight and seven Note A Clear overrides load data and count inputs Note B When counting up count down input must be high when counting down count-up input must be high
4
Schematic Diagrams
MM54C192 Synchronous 4-Bit Up Down Decade Counter
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TL F 5901 - 6
MM54C193 Synchronous 4-Bit Up Down Binary Counter
TL F 5901 - 7
5
MM54C192 MM74C192 Synchronous 4-Bit Up Down Decade Counter MM54C193 MM74C193 Synchronous 4-Bit Up Down Binary Counter
Physical Dimensions inches (millimeters)
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Ceramic Dual-In-Line Package (J) Order Number MM54C192J MM74C192J MM54C193J or MM74C193J NS Package Number J16A
Molded Dual-In-Line Package (N) Order Number MM54C192N MM74C192N MM54C193N or MM74C193N NS Package Number N16E LIFE SUPPORT POLICY NATIONAL'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL SEMICONDUCTOR CORPORATION As used herein 1 Life support devices or systems are devices or systems which (a) are intended for surgical implant into the body or (b) support or sustain life and whose failure to perform when properly used in accordance with instructions for use provided in the labeling can be reasonably expected to result in a significant injury to the user
National Semiconductor Corporation 1111 West Bardin Road Arlington TX 76017 Tel 1(800) 272-9959 Fax 1(800) 737-7018
2 A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system or to affect its safety or effectiveness
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National does not assume any responsibility for use of any circuitry described no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications

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